Copper pouring on PCB

Copper pouring is a technique used in printed circuit board (PCB) design where large areas have to be filled with copper. This process creates a "flood" of copper in specific regions, serving several important functions in the design and functionality of the PCB.

Many ECAD software programs offer a copper filling function, usually applied after routing is complete. However, using this function only at the end of the design is a mistake. Copper pouring should not be used solely for saving copper: filling gaps with ground areas is the best way to enhance EMC performance, protect traces from interference, and improve thermal management.

Do not leave copper pouring and ground copper areas pouring as the last action at the end of your design. Instead, consider these elements since the earliest stages, even before you start the routing. Additionally, pay attention to the pouring strategy: choose precisely which traces to protect, which electrical nets you want to use for filling the areas, and how to connect them across layers. Options include ground, shielding areas, radiofrequency ground, as well as using multiple vias or via fencing. There are many options and, especially in systems with multiple grounds, you must select the most appropriate reference net to act as a shield.

Below are some good reasons to fill all the layers with copper.

What do you usually do when you want to protect a trace from the surrounding ones? Increasing clearances could be not enough, so shielding becomes the right strategy.

Let's examine the disruptive effect of a trace on another when a capacitive or inductive coupling is present, using a simple trace model. Radiated interference is not considered, as it would require at least a 2D solver and is beyond the scope of this article.

Capacitive coupling is due to stray capacitance between two parallel traces. If one of the two traces carries a fast switching signal, the second one could be negatively affected at every rising and falling edge. In the image on the left, you can see what happens to a victim trace when stray capacitance exists and no countermeasures are taken.

The easiest solution? Add some copper pouring between the two traces with a good connection to the ground plane. If the connection is not made properly, introducing the shielding ground shape may have no effect, or, additional ringing in case of some parasitic inductances are introduced (not considered in this example). However, from this simple example, one can see how the peak voltage in the victim trace lowers from 1.3V to 12uV! This is not a realistic case since no stray element has been considered and the trace model is kept quite simple - in a real PCB you won't get a trace or copper pouring exempt from unwanted inductances. Now, look at the next image: traces are represented using the distributed RLC model to achieve more realistic results.

Some parasitic elements have been added: the trace self-inductance and resistance, the distributed capacitance between the two traces and, in the second case (with the ground trace between victim and aggressor) the impedance between the shielding trace and the ground plane, due to vias connection. Shielding obtained through copper pouring is still effective but a ringing around 1.5GHz appears in the victim trace! This is caused by a poor connection (high impedance in the whole spectrum or at specific frequencies) between the shielding ground trace and the ground plane on the bottom layer. In this case, the solution consists of increasing the number of vias.

In the image below one can see what is meant for proper vias fencing to minimize the impedance between the ground shape on the top layer and the ground plane on the bottom layer. I'll never stop repeating: impedance between to ground (layers, traces, shapes and mechanical elements like screws, shells, shields, spring contacts and so on) must be minimized, whichever the design!

Inductive coupling occurs when two traces are drawn alongside each other. Through the mutual inductance, the aggressor induces current in the victim trace that turns into voltage spikes, offsets, superimposed waves and so on.

Again, adding copper between the traces improves the signal integrity in the victim trace, protecting it from induced currents. All the observations made for the capacitive coupling are still valid.

Filling empty areas with copper and covering them on the top and bottom layer with the ground is good from an EMC point of view too.

It's not rare to have radiated emission problems caused by poorly routed, exposed traces on your PCB. A reasonable solution before adding shielding, conductive gaskets and other costly fixes, is to redesign the PCB using copper pouring, especially on outer layers and routing planes and traces in the inner layer. Maybe this won't solve your EMC issues but it's free, so why not?

Copper has excellent thermal conductivity (400W/mK circa), so pouring copper in large areas can help to dissipate heat generated by components on the PCB. This is particularly important in high-power density applications where components generate significant heat.

Having a layout with many 'holes', i.e. copper-free FR4 areas where no component is placed, is bad because of FR4 reduced thermal conductivity: if your application needs an improved level of power dissipation, consider copper pouring for better thermal management.

Another positive aspect of copper pouring is the reduced time needed for PCB fabrication and the amount of copper lost in the process. Etching (copper removal process aimed to define traces, planes, and conductive shapes on the PCB) is a subtractive process, so the less copper you remove, the greener and faster the process is.

However, the drawback is the higher fabrication costs due to the increased number of vias required to connect copper shapes to the ground plane(s).

Look at the image aside: the first trace from the top is separated from the second one by a ground copper plane connected to the plane through a series of vias (via fencing). That is the best solution for electrical performance.

The second trace is separated from the third one by a ground copper plane, but, this time, the ground is not connected to the plane: this increases the impedance whereas the shielding effect is almost completely nullified.

Finally, the next four traces are one next to the other, with minimal clearance between them: this is the worst routing technique since the noise in the victim traces is dependent solely on the value of the stray elements (mutual capacitance and inductance). If you choose to use copper pouring in your design, take care to implement it in the right way.

In summary, copper pouring is a fundamental technique in PCB design that serves multiple critical functions, from enhancing electrical performance to improving thermal management and reducing manufacturing costs.