VHDL simulation

Let's place the three files written in previous articles in the same directory and open a terminal instance there.

Type the following two commands: if everything goes fine, you shouldn't see any output on the screen

Be sure that the name you used in entity definition is te same used as file name for both files. Now you have to create an executable containing both testbench instructions and devuce under test description; to do this, type

Now you can run the simulation and generate an output file, so type

In your working directory you should see two new files: a .cf and a .vcd file. Ignore the first one, the second one contains simulation data.

The '-fsynopsys' additional parameter is necessary since in the testbench file I imported std_logic_arith library, that is a legacy library from Synopsys.

Open GTKwave from terminal or start menu. The interface is quite intuitive, however I'll explain something here. Go to File>Open New Tab and select the .vcd file, you will see the project structure on the left tab and the simulation result on the right.

Let's take a look to to the values written in the timing diagram (if numbers are written as hex, convert them to decimal by clicking with right mous button on each of them and selecting Data Format>Decimal): you should see that Y bus follows the input 'one' or 'zero' according to the state of 'sel' signal. This is exactly how a multiplexer works: it propagates to its output the value of the selected input, discarding the other one.

Transition are made every 5ns, that is the amount of time specified in the testbench file, between one input update and the next one.